1. Field of the Invention
This invention relates to power converters and, more particularly, to incorporating power-management functions in power converters.
2. Description of the Related Art
From 1995 to 2001, the highest density processors from manufacturers such as Intel went from a power consumption rate of about 30 Watts at 3.3 V to a power consumption rate of about 90 Watts delivered at 1.5 V. A simple application of the power-voltage-current relationship reveals that the total current consumed by these chips has increased from nine amps to about 60 amps in a very short time period. There are similar analogies with all larger digital integrated circuits (ICs).
This rapid evolution has created new and significant problems in delivery of the power to and removal of waste heat from these ICs. Power supply design is now a much more critical and difficult task than it was a few years ago. High-current/low-voltage ICs require a very clean and stable source of DC power. The power source must be capable of delivering very fast current transients. The electronic path to these loads must also have low resistance and inductance (a 1.5V supply would be completely dropped across a 25 mΩ resistance at 60 Amps).
Traditionally, DC power supplies were designed to convert AC line voltage to one or more DC outputs that would be routed throughout a system to the points of load (POL). FIG. 1 is an illustration of a prior art power distribution system. As shown in FIG. 1, a power distribution scheme 100 may comprise an AC to DC converter 102 generating output voltages V1, V2, V3, and V4 that may be distributed to various point of load devices (POLs). However, it may not be practical to route high-current signals throughout a system.
To overcome this difficulty, and to reduce the ill effects of distributing high current signals around a system, an alternative method of distributing power at modest voltage and current levels has been adopted. Rather than converting an AC supply voltage level to the DC voltage level required by various loads at a central location, the AC supply voltage is typically converted to a “reasonable” DC voltage and routed to the “point of load” (POL), where it is converted locally to the required low voltage. This technique is referred to as “Distributed Power Architecture”, or DPA, and is illustrated in FIG. 2. As shown in DPA system 200 of FIG. 2, an AC to DC voltage converter 202 may produce an intermediate DC voltage Vx, which may be routed to individual local DC to DC converters 204, 206, 208, and 210, which in turn may provide the required DC voltages V1, V2, V3, and V4, respectively, to their corresponding POLs. With a DPA, errors may be reduced since the distance traveled by a high-current signal is minimized, thus reducing I×R (resistive) and L di/dt (inductive) errors.
In many power distribution systems it is typically not enough to just distribute power around a system to the various POLs. Complex electronic systems are generally monitored and controlled to ensure maximum reliability and performance. Functions (power supply features) typically implemented in DPA systems are listed below.
Supply Sequencing
A modern electronic system can contain many ICs and each IC can have several supply voltage requirements. For example, core logic may require one voltage and the I/O may require a different voltage. This typically results in a need for setting the order in which the voltages on a single chip are applied and the order in which the chips in a system are powered up.
Hot Swap
Many electronic systems, including computers, telecom racks, storage devices and battery-operated devices require “hot swap” capability. Hot swap capability typically comprises the live attachment of a device to power, i.e., attaching a device to a system that is powered up (without having to power down the system prior to the attachment). Examples of hot swap events may include installing a battery in a PDA or plugging a USB device into a computer.
Ramp Control
It is sometimes necessary to control the rate at which the DC output voltage of a converter ramps from its initial value to its nominal value. This may be done in support of managing a hot-swap event, sequencing requirement or satisfying the requirements of the load.
Voltage Programming
The final voltage presented to a load may need to be programmed to the desired value or may need to be “trimmed” to a precise value. Some systems require active voltage programming of devices during their use.
Load Monitoring
In order to maintain high reliability of an electronic system, monitoring of load status is sometimes required. Both current and voltage may need to be monitored and action may need to be taken based on the load status measurements. Current and voltage may also need to be monitored for undershoot and overshoot conditions. In some systems, when an error is detected, the system may take corrective action by switching the load off, isolating the load or just setting a system flag.
Tracking
Many times it is desirable to have the output of one more converters follow, or mirror, the output of one or more other converters in the system. Tracking a specific voltage level, for example, may include setting the voltage level of a tracking converter or device to the voltage level of a tracked converter or device, and changing the voltage level of the tracking device to match the voltage level of the tracked device any time the voltage level of the tracked device changes. In some cases the voltage levels of tracking devices and tracked devices may not be the same; changes in the tracked voltage level would simply be mirrored in the voltage output of the tracking devices. For example, if the tracked voltage increases by 0.2V, the tracking voltage would also increase by 0.2V.
Temperature Monitoring
Dense electronic systems often generate excessive waste heat. The excessive heat generally needs to be removed in order to keep the electronics operating at their safe operating temperature. Therefore, the temperature of individual loads as well as the temperature of various locations within the system's enclosure is typically monitored. When temperatures reach unacceptable limits, action may need to be taken locally and/or at the system level. Such corrective actions often include turning on or speeding up fans, setting an alarm or simply shutting down the power to the problematic load. Temperatures can be measured using several methods. Some large digital processors sometimes incorporate embedded temperature sensor diodes on chip. Other systems may employ thermistors and IC temperature sensors.
Fan Speed Control
In conjunction with temperature monitoring it is often necessary to monitor and control fan speed. This may be done to control airflow or to control acoustic noise.
Phase Control
DC voltage is typically stepped down in one of two ways, linear regulation and DC-to-DC conversion. DC-to-DC converters may step down DC voltage by pulse width modulation (PWM) of an input voltage and passive filtering of the output. The duty cycle of the PWM signal generally approximates the ratio of output voltage to input voltage divided by the efficiency of the converter. For example, for an ideal DC-to-DC converter with a desired output of 1.2V and an input of 12V, the duty cycle would be 10%. In high current applications, it is often desirable to force the various DC-to-DC converters to sample different “phases” of their clock cycle. That is, to prevent DC-to-DC converters in a system from all sampling the first 10% of a clock cycle, one converter may sample the first 10% of the clock cycle and the next converter may sample a different 10% of the clock cycle, and so on. This typically reduces noise and improves transient response. This technique is also used in motor control and is often implemented to control multiple fans in a system. PWM controlled fans with staggered phase typically offer reduced acoustic noise.
Current Sharing
In addition to forcing DC-to-DC converters to sample staggered phases of the switching clock, it is sometimes desirable to force two or more independent converters to each deliver an equal share of the load current. This approach provides improved noise and transient response in high-current applications.
Programmable Switching Frequency
Certain DC-to-DC converters feature programmable switch frequencies. Frequencies may be selected based on several system concerns.
Synchronization of Switching Clocks
It is often desirable to synchronize the switching frequency of DC-to-DC converters in a system to each other or to some other system clock. This is typically performed to reduce the probability of mixing the clock or its harmonics with important system clocks. It is of particular interest in communication applications.
There are other functions that may be required for power systems. For example, single points of temperature measurement, open/closed status of doors and vibration may be of interest.
In order to accommodate a demand for more power and denser systems and the resulting new distribution problems, many present power distribution schemes began offering multiples of each solution, or functions, in a single package. Typically each of these functions requires a separate configuration within the system. That is, each function may require its own interconnection network tying the POL converters together. The interconnection network may implement glue-logic that may be required for control of the POL converters in order for the particular function to be successfully executed during system operation. Many of these functions comprise analog signal control requiring corresponding analog signal lines, with POL converters interconnected in point-to-point configurations. Routing of such signals is often difficult, while no true communication is established between various POL converters and/or between the POL converters and any other elements of the system.
In an effort to tie all or most of these functions together at the system level, one approach has been to implement the functions in control ICs responsible for controlling respective POL converters. Some of the functionality may also be programmed into a microcontroller that may communicate with attached POL converters over an I2C (inter-IC communication) bus to coordinate control of all POL converters in the system. FIG. 3 illustrates an example of an I2C-based system. As shown in FIG. 3, a microcontroller 302 may be coupled to POL converters 320, 322, 324, and 326, with the connections between the devices representing an I2C bus. A configuration as shown in FIG. 3 is typically not suited for active control and is used mainly for status monitoring, where POL converters 320, 322, 324, and 326 may send a status signal back to microcontroller 302, which in turn may send a simple control signal to a respective POL converter based on the status information received from the respective POL converter. In general, microcontroller 302 checks status for one POL converter at a time, which may be viewed as a disadvantage when more interactive, real-time communication is desired in a system.
FIG. 4 illustrates one example of a single function implemented in a DPA system. Typically, a supply controller 350 (providing control for executing the function) and DC-to-DC voltage converters 352, 354, 356, and 358 are connected in a point-to-point configuration as shown. Supply controller 350 is coupled to each DC-to-DC converter over dedicated lines, (typically analog lines are used for implementing most functions), more specifically over lines 372 and 362 to converter 352, lines 374 and 364 to converter 354, lines 376 and 366 to converter 356, and lines 378 and 368 to converter 358. Input supply voltage VIN 360 is coupled to each DC-to-DC converter, and in turn DC-to-DC converter 352 may produce, for a respective POL or POLs, DC output voltage 370, DC-to-DC converter 354 may produce DC output voltage 372, DC-to-DC converter 356 may produce DC output voltage 374, and DC-to-DC converter 358 may produce DC output voltage 376.
DC-to-DC conversion is often performed by switching power regulators, or step-down regulators, converting a higher voltage (e.g. 12V) to a lower value as required by one or more load devices. A common architecture features distribution of the higher voltage to multiple power regulators, each producing a different (or possibly the same) voltage to one or more loads. Switching power regulators often use two or more power transistors to convert energy at one voltage to another voltage. One common example of such a power regulator, commonly called a “Buck Regulator” is shown in FIG. 5. A Buck Regulator typically switches a pair of power transistors (408 and 410) in order to produce a square-wave at their common node SW. The produced square-wave can be smoothed out using an LC circuit comprising inductor 412 and capacitor 414 to produce the desired voltage, Vout. A control loop, comprised of an Error Amplifier 416, a Proportional-Integral-Differential (PID) Filter 402, a Pulse-Width-Modulator (PWM) 404, and an Overlap Control circuit 406, can be configured to control the duty-cycle of the output square-wave, and hence the resulting value of Vout. In general, transistors 408 and 410 are controlled such that they do not conduct current at the same time. Typically, when transistor 408 is turned on (HS is asserted), transistor 410 is turned off (LS is de-asserted). However, depending on the details of the power stage and its load, the efficiency of the regulator can be improved by careful control of the relationship between the two gate control signals, HS and LS.
FIG. 6 illustrates a simple timing diagram for a Buck Regulator, such as the regulator shown in FIG. 5. As shown in FIG. 6, a brief “deadtime” is generated between transistor 408 being disabled—shown as HS signal 440 de-asserting from a high value to a low value—and transistor 410 being enabled—shown as LS signal 442 asserting from a low value to a high value. The period during which both devices are turned off generally eliminates the possibility of their conducting current directly from the input to ground. If the deadtime is too short, such cross-conduction could waste power. However, if the deadtime is too long, the body-diode of transistor 410 may conduct current, and may thus also waste power. One aspect of deadtime control is the optimization of the timing to obtain greater efficiency, that is, the highest possible ratio of the output power to the input power (Pout/Pin). Depending on the specifics of any given design, the optimal deadtime could require that the gate control signals slightly overlap.
One common method for controlling the deadtime in power converters includes using a simple detection circuit for determining when a transistor has been disabled. One example of a simple detection circuit—which is also often used to allow the other transistor to enable—is shown in FIG. 7. The input to the circuit may be a control signal generated by PWM circuit 404. When the PWM signal is asserted (in this case having a high value), transistor 408 may be expected to enable. However, the circuit generally inhibits transistor 408 until transistor 410 has responded to the PWM signal, to turn-off. More specifically, a gate control signal is not asserted until the opposite gate control signal has been de-asserted. This typically guarantees that the two gate control signals (HS and LS) will never overlap. The deadtime, that is, the length of time during which both control signals HS and LS are de-asserted, is controlled by delay cells 430 and 432. Often implemented as a series of logic gates, delays 430 and 432 can generally be controlled to tune the desired deadtime. However, since only the command gate control signal is detected, the actual transistor response for a transistor having significant gate impedance can lag behind the gate signal, and hence shorten the actual deadtime. Several methods to solve this problem have been implemented. Some circuits use additional package pins to allow a direct connection to the transistor gate in order to provide a sense path for the circuits. While this may help solve driver and board impedance issues, it does not address the issue of the transistor gate impedance. Another technique includes measuring the current being supplied by the HS and LS driver outputs as they charge the transistor gates. When the current approaches zero, it may be taken as an indication that a given transistor has responded to the gate control, and the other transistor may then be allowed to change state.
Many other problems and disadvantages of the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.